> For the complete documentation index, see [llms.txt](https://docs.pmem.io/ndctl-user-guide/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://docs.pmem.io/ndctl-user-guide/cxl-man-pages/cxl-enable-port-1.md).

# cxl-enable-port(1)

## NAME&#x20;

cxl-enable-port - activate / hot-add a given CXL port

## SYNOPSIS&#x20;

cxl disable-port \<port0> \[\<port1>..\<portN>] \[\<options>]

A port typically autoenables at initial device discovery. However, if it was manually disabled this command can trigger the kernel to activate it again. This involves detecting the state of the HDM (Host Managed Device Memory) Decoders and validating that CXL.mem is enabled for each port in the device’s hierarchy.

## OPTIONS&#x20;

-e, --endpoint

&#x20;   Toggle from treating the port arguments as Switch Port identifiers to Endpoint Port identifiers.

-m, --enable-memdevs

&#x20;   Try to enable descendant memdevs after enabling the port. Recall that a memdev is only enabled after all CXL ports in its device topology ancestry are enabled.

\--debug&#x20;

&#x20;   If the cxl tool was built with debug disabled, turn on debug messages.

## COPYRIGHT&#x20;

Copyright © 2016 - 2022, Intel Corporation. License GPLv2: GNU GPL version 2 <http://gnu.org/licenses/gpl.html>. This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law.

## SEE ALSO&#x20;

[cxl-disable-port(1)](/ndctl-user-guide/cxl-man-pages/cxl-disable-port-1.md)


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