# NDCTL User Guide

## Introduction

`ndctl` is a utility for managing the Linux LIBNVDIMM Kernel subsystem. It is designed to work with various non-volatile memory devices (NVDIMMs) from different vendors. The LIBNVDIMM subsystem defines a kernel device model and control message interface for platform NVDIMM resources like those defined by the [ACPI v6.0](http://www.uefi.org/sites/default/files/resources/ACPI_6_0_Errata_A.PDF) NFIT (**N**VDIMM **F**irmware **I**nterface **T**able). The latest [ACPI ](http://www.uefi.org/specifications)and [UEFI ](http://www.uefi.org/specifications)specifications can be found at [uefi.org](http://www.uefi.org). Operations supported by `ndctl` include:

* Provisioning capacity (namespaces)
* Enumerating Devices
* Enabling and Disabling NVDIMMs, Regions, and Namespaces
* Managing NVDIMM Labels

## What's new in v73

This release incorporates functionality up to the 5.17 kernel.

Highlights include full CXL topology walk and filtering in cxl-list, a new cxl-cli command to set memdev partitioning info, several unit test fixes, conversion of the build system to meson, smart error injection enhancements for 'papr' NVDIMMs, and RPM spec fixes to support config file migration, and flatpak builds.

**Commands:**&#x20;

* cxl-list: full topology walk and filtering&#x20;
* cxl-set-partition: new command to set memdev partitions&#x20;
* cxl{enable,disable}-port: new commands&#x20;
* cxl{enable,disable}-memdev: new commands

**Tests:**&#x20;

* Deprecate BLK aperture support&#x20;
* inject-smart.sh: increase tolerance for decimal formatted fields

**APIs:**&#x20;

* ndctl\_dimm\_refresh\_flags&#x20;
* cxl\_bus\_get\_ctx&#x20;
* cxl\_bus\_get\_devname&#x20;
* cxl\_bus\_get\_first&#x20;
* cxl\_bus\_get\_id&#x20;
* cxl\_bus\_get\_next
* cxl\_bus\_get\_port&#x20;
* cxl\_bus\_get\_provider&#x20;
* cxl\_cmd\_identify\_get\_persistent\_only\_size
* cxl\_cmd\_identify\_get\_total\_size&#x20;
* cxl\_cmd\_identify\_get\_volatile\_only\_size&#x20;
* cxl\_cmd\_new\_get\_partition&#x20;
* cxl\_cmd\_new\_set\_partition&#x20;
* cxl\_cmd\_partition\_get\_active\_persistent\_size&#x20;
* cxl\_cmd\_partition\_get\_active\_volatile\_size&#x20;
* cxl\_cmd\_partition\_get\_next\_persistent\_size&#x20;
* cxl\_cmd\_partition\_get\_next\_volatile\_size&#x20;
* cxl\_cmd\_partition\_set\_mode&#x20;
* cxl\_decoder\_get\_ctx&#x20;
* cxl\_decoder\_get\_devname&#x20;
* cxl\_decoder\_get\_first&#x20;
* cxl\_decoder\_get\_id&#x20;
* cxl\_decoder\_get\_next&#x20;
* cxl\_decoder\_get\_nr\_targets&#x20;
* cxl\_decoder\_get\_port&#x20;
* cxl\_decoder\_get\_resource&#x20;
* cxl\_decoder\_get\_size&#x20;
* cxl\_decoder\_get\_target\_by\_memdev&#x20;
* cxl\_decoder\_get\_target\_by\_position&#x20;
* cxl\_decoder\_get\_target\_type&#x20;
* cxl\_decoder\_is\_accelmem\_capable&#x20;
* cxl\_decoder\_is\_locked&#x20;
* cxl\_decoder\_is\_mem\_capable&#x20;
* cxl\_decoder\_is\_pmem\_capable&#x20;
* cxl\_decoder\_is\_volatile\_capable&#x20;
* cxl\_dport\_get\_devname&#x20;
* cxl\_dport\_get\_first&#x20;
* cxl\_dport\_get\_id&#x20;
* cxl\_dport\_get\_next&#x20;
* cxl\_dport\_get\_physical\_node&#x20;
* cxl\_dport\_get\_port&#x20;
* cxl\_dport\_maps\_memdev&#x20;
* cxl\_endpoint\_get\_bus&#x20;
* cxl\_endpoint\_get\_ctx&#x20;
* cxl\_endpoint\_get\_devname&#x20;
* cxl\_endpoint\_get\_first&#x20;
* cxl\_endpoint\_get\_host&#x20;
* cxl\_endpoint\_get\_id&#x20;
* cxl\_endpoint\_get\_memdev&#x20;
* cxl\_endpoint\_get\_next&#x20;
* cxl\_endpoint\_get\_parent&#x20;
* cxl\_endpoint\_get\_port&#x20;
* cxl\_endpoint\_is\_enabled&#x20;
* cxl\_memdev\_disable\_invalidate&#x20;
* cxl\_memdev\_enable&#x20;
* cxl\_memdev\_get\_bus&#x20;
* cxl\_memdev\_get\_endpoint&#x20;
* cxl\_memdev\_get\_host&#x20;
* cxl\_memdev\_get\_numa\_node&#x20;
* cxl\_memdev\_get\_serial&#x20;
* cxl\_memdev\_is\_enabled&#x20;
* cxl\_port\_disable\_invalidate&#x20;
* cxl\_port\_enable&#x20;
* cxl\_port\_get\_bus&#x20;
* cxl\_port\_get\_bus&#x20;
* cxl\_port\_get\_ctx&#x20;
* cxl\_port\_get\_devname&#x20;
* cxl\_port\_get\_dport\_by\_memdev&#x20;
* cxl\_port\_get\_first&#x20;
* cxl\_port\_get\_host&#x20;
* cxl\_port\_get\_id&#x20;
* cxl\_port\_get\_next&#x20;
* cxl\_port\_get\_next\_all&#x20;
* cxl\_port\_get\_nr\_dports&#x20;
* cxl\_port\_get\_parent&#x20;
* cxl\_port\_hosts\_memdev&#x20;
* cxl\_port\_is\_enabled&#x20;
* cxl\_port\_is\_endpoint&#x20;
* cxl\_port\_is\_root&#x20;
* cxl\_port\_is\_switch&#x20;
* cxl\_port\_to\_bus&#x20;
* cxl\_port\_to\_endpoint&#x20;
* cxl\_target\_get\_decoder&#x20;
* cxl\_target\_get\_devname&#x20;
* cxl\_target\_get\_first&#x20;
* cxl\_target\_get\_id
* cxl\_target\_get\_next&#x20;
* cxl\_target\_get\_physical\_node&#x20;
* cxl\_target\_get\_position&#x20;
* cxl\_target\_maps\_memdev


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