> For the complete documentation index, see [llms.txt](https://docs.pmem.io/ndctl-user-guide/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://docs.pmem.io/ndctl-user-guide/cxl-man-pages/cxl-disable-port-1.md).

# cxl-disable-port(1)

## NAME 

cxl-disable-port - activate / hot-add a given CXL port

## SYNOPSIS 

cxl disable-port \<port0> \[\<port1>..\<portN>] \[\<options>]

For test and debug scenarios, disable a CXL port and any memory devices dependent on this port being active for CXL.mem operation.

## OPTIONS&#x20;

-e, --endpoint

&#x20;   Toggle from treating the port arguments as Switch Port identifiers to Endpoint Port identifiers.

-f, --force&#x20;

&#x20;   DANGEROUS: Override the safety measure that blocks attempts to disable a port if the tool determines a descendent memdev is in active usage. Recall that CXL memory ranges might have been established by platform firmware and disabling an active device is akin to force removing memory from a running system.

&#x20;   Toggle from treating the port arguments as Switch Port identifiers to Endpoint Port identifiers.

\--debug&#x20;

&#x20;   If the cxl tool was built with debug disabled, turn on debug messages.

## COPYRIGHT&#x20;

Copyright © 2016 - 2022, Intel Corporation. License GPLv2: GNU GPL version 2 <http://gnu.org/licenses/gpl.html>. This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law.

## SEE ALSO&#x20;

[cxl-enable-port(1)](/ndctl-user-guide/cxl-man-pages/cxl-enable-port-1.md)